E0 223: Automated Verification


January - April 2011
Instructor: Aditya Kanade
Office Hours: Wednesdays: 5pm - 6pm
(by prior email appointment)
TAs: Anirudh Santhiar, Pranavadatta D.N.
Timings:
Tuesdays: 3.30pm - 5pm
Thursdays: 3.30pm - 5pm
Classroom: 117



Announcements



Introduction


Computer systems in today's world are large, complex, costly, and perhaps safety-critical. Their correctness is as critical as their performance. While testing is an indispensable technique for exploring behaviors of systems, it can rarely cover all behaviors of the system. Many bugs still make it past testing. Automated verification is an alternative to testing wherein a mathematical model of a system is built and analyzed, algorithmically, with respect to logical specifications. Some examples of successful applications of verification to real world systems are IEEE Futurebus+ cache coherence protocol, primary flight control software of Airbus A340, and Windows device drivers.

In this course, we will discuss formal modeling of systems and logical specifications of their properties. Our focus will be on understanding the core algorithmic techniques for formal analysis.

Course contents



Course evaluation



Reference texts



Slides and other material


The slides on propositional and first-order logic are adapted from slides available here. The slides on temporal logic are adapted from slides available here.